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bob体育官网-bob体育最新版下载地址

罗小蓉

邮箱:xrluo@uestc.edu.cn
电话:028-61831559
系别:微电子与固体电子系
职称:教授
教师个人主页:http://faculty.uestc.edu.cn/luoxiaorong
教师简介
教育背景
2007年,bob体育最新版下载地址,博士学位
2001年,四川大学,硕士学位
工作履历
2001年7月-至今,bob体育最新版下载地址工作;
2009-2010年到英国剑桥大学进行博士后研究;
2011年聘为博士生导师,2012年破格晋升教授;
现任微电子与固体电子学系主任。

学术兼职

1、IEEE international symposium on power semiconductor devices & ICs 的Technical programe Committee (TPC)委员(ISPSD是全球功率半导体领域最高级别专业学术会议)
2、IEEE EDS Power Devices and ICs,全球15名Technical Committee委员之一
3、Advances in Material and Physics of Power Semiconductor and Integration,Guest Editor
4、NMCI国际会议,大会Co-chair
5、担任国际权威期刊IEEE EDL,IEEE TED, IEEE Power Electronics Lett.,IEEE Tran. Power Electronics, Solid-State Electronics以及Microelectronics Journal等国际期刊的审稿人;连续多年被IEEE Electron Device Society邀请参加IEEE EDL、IEEE TED期刊Reviewer,并获Golden Reviewers
6、国家自然科学基金通讯评审专家;
7、国际会议IEEE ICSICT分会主席;
8、四川省电力电子节能技术与装备重点实验室学术委员会委员;
9、四川省电力电子学会学术委员会副主任。

荣誉奖励

2010年,国家科技进步二等奖;
2011年,教育部新世纪优秀人才支持计划;
2016年,四川省科技进步一等奖;
2014年,教育部自然科学奖二等奖;
2013年,四川省青年科技奖;
2013年,四川省学术技术带头人后备人选;
2011年,四川省优秀博士学位论文
2012年,bob体育最新版下载地址百人计划
2016年,本科教学优秀奖
2017年,“优秀科技工作者”(中国电子学会颁发)
2017年,bob体育最新版下载地址先进工作者
2017年,bob体育最新版下载地址第四届“我最喜爱老师”卓越风采奖
科学研究

代表性学术成果(部分):


(一)学术论文

行业顶级期刊IEEE EDL和IEEE TED共29篇

[1] Kun Zhou, Linhua Huang, Xiaorong Luo*, Zhaoji Li; Bo Zhang.Characterization and Performance Evaluation of the Superjunction RB-IGBT in Matrix Converter,IEEE Transactions on Power Electronics, DOI: 10.1109/TPEL.2017.2709323,2018.

[2] Jie Wei;Xiaorong Luo*; Linhua Huang; Bo Zhang,Simulation Study of a Novel Snapback-Free and Low Turn-Off Loss Reverse-Conducting IGBT With Controllable Trench Gate IEEE Electron Device Lett.,DOI: 10.1109/LED.2017.2780081,2018.

[3] Gaoqiang Deng, Xiao Rong Luo, Jie Wei et al.A Snapback-Free Reverse Conducting Insulated-Gate Bipolar Transistor With Discontinuous Field-Stop Layer,IEEE Transactions on Electron Devices,DOI: 10.1109/TED.2018.2817204, 2018.

[4] linhua Huang;Xiaorong Luo*; Jie Wei; Kun Zhou et al;A Snapback-Free Fast-Switching SOI LIGBT With Polysilicon Regulative Resistance and Trench Cathode,IEEE Transactions on Electron Devices,DOI: 10.1109/TED.2017.2726080,2017. 

[5] Weiwei Ge, Xiaorong Luo*, Junfeng Wu,et al.Ultra-low On-Resistance LDMOS with Multi-plane Electron Accumulation Layers,IEEE Electron Device Lett., DOI: 10.1109/LED.2017.2701354,2017.

[6] Xiaorong Luo, Qiao Tan,Jie Wei,Kun Zhou,Gaoqiang Deng,Zhaoji,Ultralow On-Resistance High Voltage p-channel LDMOS with an Accumulation-Effect Extended Gate, IEEE Transactions on Electron Devices, 63(6), p.2614, 2016.

[7] Xiaorong Luo*, Da Ma, Jie Wei , et al. A split gate power FINFET with improved on-resistance and switching performance, IEEE Electron Device Lett.,37(9),p.1185, 2016.

[8] Xiaorong Luo*, Mengshan Lv, et al. Ultralow On-Resistance SOI LDMOS with Three Separated Gates and High-K Dielectric, IEEE Transactions on Electron   Devices, 66(9), p.3804, 2016.

[9] Kun Zhou, Xiaorong Luo*, Linhua Huang, et al.,An Ultralow Loss Superjunction Reverse Blocking Insulated-Gate Bipolar Transistor with Shorted-Collector Trench,DOI: 10.1109/LED.2016.2613638, 2016.

[10] Jie Wei , Xiaorong Luo*, Yanhui Zhang,Pengcheng Li,Kun Zhou,Bo Zhang,Zhaoji Li, High Voltage Thin SOI LDMOS with Ultralow On-resistance and EvenTemperature Characteristic,IEEE Transactions on Electron Devices, 63(4),p.1637, 2016.

[11] Kun Zhou, Xiaorong Luo*, Qing Xu, et al. Analytical Model and New Structure of the Variable-k Dielectric Trench LDMOS with Improved, IEEE Transactions on Electron Devices, 62(10), p.3334, 2015.

[12] Xiaorong Luo, Y H Jiang, K Zhou, Bo Zhang et al. Ultra-low Specific On-Resistance Superjunction Vertical DMOS with High-K Dielectric Pillar, IEEE Electron Device Lett., 33(7) ,1042-1044, 2012.

[13] Xiaorong Luo, J Fan, Bo Zhang Florin Udrea, Ultra-low Specific On-Resistance High Voltage SOI Lateral MOSFET, IEEE Electron Device Lett., 32(2), 185-187, 2011.

[14] Xiaorong Luo, Yuangang Wang, Guoliang Yao, et al, High Voltage Partial SOI LDMOS with a Variable Low-k Dielectric Buried Layer and a Buried P-layer, IEEE Electron Device Lett., 31(6), 594-596, 2010.

[15] Xiaorong Luo, Tianfei Lei, Bo Zhang, et al. A high-voltage LDMOS compatible with high voltage integrated circuits on p-type SOI layer, IEEE Electron Device Lett.,30(10),1093-1095, 2009.

[16] Xiaorong Luo, Zhaoji Li, Bo Zhang, et al. Realization of High Voltage ( >700V) in New SOI Devices with a Compound Buried-Layer, IEEE Electron Device Lett.,29(12),pp.1395-1397, 2008.

[17] Xiaorong Luo, Bo Zhang, Zhaoji Li, et al. A Novel 700-V SOI LDMOS with Double-Sided Trench, IEEE Electron Device Lett., 28(5): 422-424, 2007.

[18] Xiaorong LuoJie Wei,Xianlong Shi,Kun Zhou,Ruichao Tian,Zhaoji Li,Bo Zhang ,Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage, IEEE Trans.on Electron Devices, 2014,61(12):4304-4308.

[19] Xiaorong Luo, J Y Cai, Y Fan,et al. Novel Low-Resistance Current path UMOS with High-K Dielectric Pillars,IEEE Trans. Electron Devices, 60(9), 2840-2846, 2013.

[20] Xiaorong Luo, T F Lei, Y. G. Wang. Low On-Resistance SOI Dual Trench- Gates MOSFET,IEEE Trans. on Electron Devices, 59(2), 504-509, 2012.

[21] Xiaorong Luo, H Deng, Y G Wang, Novel Low-k Dielectric Buried Layer High Voltage LDMOS on Partial SOI, IEEE Tran. Electron Devices, 57(2), pp.535-538, 2010.

[22] Xiaorong Luo, Bo Zhang, Tianfei Lei, Florin Udrea, et al, Numerical and Experimental Investigation on a Novel High Voltage SOI LDMOS in the self- isolation HVIC, IEEE Tran. Electron Devices, 57(11), pp. 3033-3043, 2010.

[23] Xiaorong Luo, Daping Fu, Lei Lei et al. Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure, IEEE Tran. Electron Devices, 56(8),pp.1659-1666, 2009.

[24] Xiaorong Luo, Bo Zhang, Zhaoji Li. New high voltage (>1200V) MOSFET with the chargeTrenches on Partial SOI,IEEE Tran. Electron Devices, 2008, 55(7), 1756-1761.

[25] Kun Zhou, Xiaorong Luo*, Qing Xu, et al. A RESURF-Enhanced P-Channel SOI LDMOS with Ultralow Specific On-Resistance,IEEE Tran. Electron Devices, 61(7),2466 -2472, 2014.

[26] Wentong Zhang,Bo Zhang,Ming Qiao, Zehong Li, Xiaorong Luo,Zhaoji Li.   Optimization of Lateral Superjunction Based on the Minimum Specific ON-Resistance, IEEE Tran. Electron Devices,DOI: 10.1109/TED.2016.2542263,2016.

[27] Wentong Zhang, Bo Zhang, Ming Qiao, Zehong Li, Xiaorong Luo, Zhaoji Li. Optimization and New Structure of Superjunction With Isolator Layer, IEEE Tran. Electron Devices,DOI: 10.1109/TED.2016.2628056,2017

[28]Wentong Zhang,Bo Zhang,Ming Qiao, Zehong Li, Xiaorong Luo,Zhaoji Li.  The Ron.min of Balanced Symmetric Vertical Super Junction Based on R-Well model.IEEE Tran. Electron Devices, DOI: 10.1109/TED.2016.2632113, 2017.

[29] Wentong Zhang; Zhenya Zhan; Yang Yu; Shikang Cheng; Yan Gu; Sen Zhang; Xiaorong Luo, et al.

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI, IEEE Electron Device Letters, DOI: 10.1109/LED.2017.2751571,2018.



其它国内外部分重要期刊(SCI收录)

[30] Xiaorong Luo, Wei Zhang, Zhaoji Li, et al. A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with step thickness drift region, Semiconductor Science and technology, 2008, 23 (3):No.035028.

[31] Xiaorong Luo, Bo Zhang, Zhaoji Li. A New Structure and its Analytical Model for the Electric Field and Breakdown Voltage of SOI High Voltage Device with Variable-k Dielectric Buried Layer,Solid-State Electronics,2007,51:493-499.

[32] Xiaorong Luo, Bo Zhang, Zhaoji Li. A new SOI high voltage device with step thickness sustained voltage layer.Electronics Lett. 2008, 44 (1). 入选Electronics Letters大中华地区“精选特刊”,该特刊从大中华地区于2005-2008年期间在Electronics Letters发表的论文中精选

[33] Luo Xiao-Rong, Luo Yin-Chun, Fan Ye, et al., A low specific on-resistance SOIMOSFET with dual gates and a recessed drain, Chin. Phys. B, 22(2), 027304, 2013.

[34]Luo Xiao-Rong, Wang Qi, Yao Guo-Liang, A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch,Chin. Phys. B, 22 (2),027303, 2013.

[35] Luo Xiao-Rong, G L Yao, Y G Wang, et al, A low on-resistance triple RESURF SOILDMOS with planar and rench gate integration,Chin. Phys. B, 21(2), 068501, 2012.

[36] Luo Xiao-Rong, Wang Yuan-Gang, Deng Hao, and Florin Udrea, A Novel Partial Silicon-On-Insulator High Voltage LDMOS with Low-k Dielectric Buried Layer, Chinese Physics B, 19(7), 077306-1-6, 2010.

[37] Luo Xiao-Rong, Yao Guo-liang, Wang Yuan-Gang, et al.Ultra-low On-Resistance High Voltage (>600) SOI MOSFET with a Reduced Cell Pitch, Chinese Physics B, 20(2):028501, 2011.

[38] Shi Xian-Long,Luo Xiao-Rong*(通信作者),Wei Jie,Tan Qiao ,A novel LDMOS with a junction field plate anda partial N-buried layer ,Chinese.Physics.B,2014,23(12).精选为该期的High lights论文,并 在英国物理学会出版社(IOPP)网站的Featured Articles 专栏。

[39]Li Peng-Cheng, Luo Xiao-Rong*(通信作者), Luo Yin-Chun, Zhou Kun,An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer,Chinese.Physics.B, 24(4): 047304, 2015

[40] Luo Yin-Chun,Luo Xiao-Rong*(通信作者), Hu Gang-Yi,Fan Yuan-HangA low specific on-resistance SOI LDMOS with a novel junction field plate ,Chinese.Physics.B,23(7), 2014

[41] Wang pei,  Luo Xiao-Rong*(通信作者), Ultra-low specific on-resistance vertical double-diffused metal oxide semiconductor with a high-k dielectric-filled extended trench, Chin. Phys. B, 22( 2), 027305, 2013.

[42] Zhou Kun,  Luo Xiao-Rong*(通信作者), Fan Yuan-Hang et al, Low on-resistance buried current path SOI P-channel LDMOS compatible with N-channel LDMOS, Chin. Phys.B,067306, 2013.

[43] Fan Yuan-Hang, Luo Xiao-Rong*(通信作者),Wang Pei, Zhou Kun et al, A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench, Chin. Phys. Lett, 30(8),088503, 2013.

[44] 王骁玮,罗小蓉*(通信作者),尹超 等,高k介质电导增强SOI LDMOS机理与优化设计,物理学报,v62,n23,2013

[45] Luo Yin-Chun, Luo Xiao-Rong*(通信作者), Hu Gang-Yi, et al. A low specific on-resistance SOI LDMOS with a novel unction field plate,Chin. Phys. B Vol. 23, No. 7077306,2014.

[46] Li Peng-Cheng, Luo Xiao-Rong*(通信作者), Luo Yin-Chun, et al. An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer,Chin.Phys. B, Vol. 24, No. 4,047304,2015.

[47] WANG Zhuo, LI Peng-Cheng, ZHANG Bo, FAN Yuan-Hang, XU Qing, Luo Xiao-Rong*(通信作者),Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate,CHIN. PHYS. LETT. Vol.32, No. 6, 068501,2015.

[48] Wang Yuan-Gang,  Luo Xiao-Rong*(通信作者), Ge Rui, Wu Li-Juan, Chen Xi,Compound buried layer SOI high voltage device with step buried oxide, Chin. Phys. B,077304, 2011.


4 篇 功率半导体领域顶级国际会议IEEE ISPSD 及邀请报告:

[49] Gaoqiang Deng;Xiaorong Luo*;Kun Zhou;Qingyuan He;Xinliang Ruan;QingLiu;Tao Sun; Bo Zhang, A snapback-free RC-IGBT with Alternating N/P buffers,IEEE ISPSD,2017,Japan.

[50] Kun Zhou; Tao Sun; Qing Liu; Bo Zhang; Zhaoji Li; Xiaorong Luo*;A snapback-free shorted-anode SOI LIGHT with multi-segmentanode, IEEE ISPSD,2017,Japan.

[51] Xiaorong Luo; Weiwei Ge; Bo Zhang, Ultralow power loss integratable high-

voltage MOSFETs, 2017 IEEE 12th International Conference on ASIC (ASICON).

[52] Jie Wei, Xiaorong Luo*(通信作者),Yanhui Zhang, et al. Accumulation-Mode High Voltage SOI LDMOS with Ultralow Specific On-resistance, IEEE ISPSD, Hongkong, China, 9-14, May, 2015.

[53] Xiaorong Luo, Y G Wang, M Qiao, Bo Zhang, Zhaoji Li, et al. Novel High Voltage LDMOS on Partial SOI with  double-sided Charge Trenches, IEEE ISPSD, San Diego,California, USA , 23-26 May, 2011.

[54] Xiaorong Luo, Tianfei Lei, Wang Yuangang, et al. A Novel High Voltage (>700V) SOILDMOS with Buried N-layer in a Self-isolation High Voltage Integrated Circuit, IEEE ISPSD, Hiroshima, Japan, June 6, 2010.

[55]Kun Zhou, Xiaorong Luo*(通信作者), Qing Xu, et al. Ultralow Specific On-Resistance High Voltage LDMOS with a Varible-K Dielectric Trench, IEEE ISPSD,Waikoloai, USA, Jun.2014.

[56] Jie Wei, Xiaorong Luo*(通信作者), Xianlong Shi, et al. An Improved On-resistance High Voltage  LDMOS with Junction Field Plate, IEEE ISPSD, Waikoloai,USA, Jun. 2014.

[57] Xiaorong Luo*,Kun Zhou,Zhaoji Li,Bo Zhang ,Ultralow specific on-resistancetrench lateral power MOSFETS ,2014 IEEE International Conference on Solid-State and Integrated Circuit Technology,1784-1787,2014.10.28-2014.10.31。


(二)发明专利

授权 4 项美国专利

[1] Xiaorong Luo, Florin Udrea, SOI Lateral MOSFET Devices,  2013 . 授权

[2] Xiaorong Luo, Guoliang Yao, Tianfei Lei, et al. Trench-type semiconductor  power

devices,  2012. 授权

[3] Xiaorong Luo, J Y Xiong, Chao Yang, et al. Enhancement mode high electron mobility

transistor,  2016. 授权

[4] Xiaorong Luo, Weiwei Ge, Junfeng Wu, et al. Kind of Power Tri-gate  LDMOS, 2017. 授权


19项授权中国发明专利

[5] 罗小蓉,姚国亮,王元刚,张波等,一种具有高K介质槽的半导体功率器件,专利号:

ZL201110075604.9

[6] 罗小蓉,王元刚,姚国亮等,一种槽型纵向半导体器件的制造方法,专利号: ZL201110075550.6

[7] 罗小蓉,姚国亮等,超结结构和超结半导体器件的制造方法,专利号:ZL201110051879.9

[8] 罗小蓉,王元刚,姚国亮等,具有延伸沟槽的超结半导体器件的制造方法,专利号:ZL201110051878.4

[9] 罗小蓉,Florin Udrea, SOI横向MOSFET器件, 专利号:ZL201010173833.x
[10] 罗小蓉,张伟,詹瞻等,基于自隔离技术的介质场增强SOI耐压结构,专利号:200910058145.6

[11] 罗小蓉,张伟,邓浩 等,在厚膜SOI材料中形成图形化半导体埋层的方法,专利号:

ZL200910058291.9

[12] 罗小蓉,雷磊,傅达平等,双面介质槽部分SOI材料的制备方法,专利号:ZL200910058508.6

[13] 罗小蓉,张波,李肇基等,一种具有窗口的双介质SOI耐压结构及其SOI功率器件,专利号:

ZL200610022119.4

[14] 罗小蓉,姚国亮,雷天飞等,SOI横向MOSFEF器件与集成电路,专利号:ZL201110003586.3

[15] 罗小蓉,姚国亮,雷天飞,王元刚,槽型半导体功率器件,专利号:201010610944.2

[16] 罗小蓉、王沛、蔡金勇,一种槽型半导体功率器件的制造方法,专利号:ZL201210226462.6

[17] 罗小蓉,王沛,范叶,张波等.一种槽型半导体功率器件,专利号:201210226454.1

[18] 罗小蓉,周坤,范叶,张波等. 纵向功率半导体器件的制造方法, 专利号:201210306150.6

[19] 罗小蓉,周坤,姚国亮等,一种双栅功率MOSFET器件,专利号:ZL201210179867.9。

[20] 罗小蓉,蒋永恒,蔡金勇等,槽栅半导体功率器件,专利号:ZL201210220695.5。

[21] 张波,胡夏融,罗小蓉. 一种槽型功率MOSFIT器件,专利号:ZL201110097449.0

[22] 张金平,张波,邓小川,陈壮梁,叶毅,罗小蓉,李肇基.漏源双凹结构的金属半导体场效应晶体

管,专利号:ZL200710048733.2

[23] 张波,张金平,邓小川,陈壮梁,叶毅,罗小蓉,李肇基.三维槽栅金属半导体场效应晶体管,申

请号:ZL200710048732.8



16项受理中国发明专利

[22] 罗小蓉,李鹏程,田瑞超,石先龙,罗尹春,周坤,张波等,一种槽型积累层MOSFET器件 ,申请号:201410142500.9

[23] 罗小蓉,李鹏程,  田瑞超, 等. 一种具有延伸栅结构的SOI LDMOS器件[P].  请号:201410439269.X

[24] 罗小蓉,李鹏程,田瑞超,石先龙,张波等,一种槽型横向MOSFET器件的制造方法,申请号: 201410143064.7。

[25] 罗小蓉,田瑞超,徐青,石先龙,李鹏程等,张波, 具有U型延伸栅的SOI槽型LDMOS器件, 申请号: 201410142967.3

[26] 罗小蓉,田瑞超,魏杰,等. 一种横向SOI功率LDMOS器件[P]. 中国,发明专利,201410439282.5.

[27] 罗小蓉,罗尹春,周坤,张波等.一种SOI基PMOSFET功率器件,申请号:201210441287.2

[28] 罗小蓉,罗尹春,范远航,张波等.一种具有结型场板的SOI功率LDMOS器件,申请号:201310202568.7

[29] 罗小蓉   魏    杰, 熊佳云 等,一种具有自适应偏置场板的高压MOS器件,申请号:201410472165.9

[30]罗小蓉,魏    杰,罗尹春,范远航等. 一种具有结型场板的功率LDMOS器件,申请号:201310202668.X

[31]罗小蓉, 熊佳云, 杨   超, 魏杰等, 一种用于GaN基HEMT器件的自适应偏置场板,申请号:2014104715200

[32]罗小蓉, 熊佳云, 杨    超,一种具有荷电介质HEMT器件,申请号:201410596567.X

[33]罗小蓉,杨     超,熊佳云,魏杰等,一种缓冲层荷电RESURF HEMT器件,

[34]罗小蓉,尹超,刘建平等,一种槽型MOS功率器件,201410834588.0

[35]罗小蓉,王骁玮,范叶,范远航等.一种横向SOI功率半导体器件,申请号:    201310346866.3

[36] 罗小蓉,徐青,周坤,田瑞超,魏杰,石先龙,张波,一种SOI横向功率MOSFET器件, 申请号: 201410143075.5

[37] 罗小蓉,蒋永恒,罗尹春,张波等. 一种横向SOI功率器件,申请号:201210271058.0


(三)荣誉和奖励

2010年,国家科技进步二等奖;

2011年,教育部新世纪优秀人才支持计划;

2016年,四川省科技进步一等奖;

2014年,教育部自然科学奖二等奖;

2013年,四川省青年科技奖;

2013年,四川省学术技术带头人后备人选;

2011年,四川省优秀博士学位论文

2012年,bob体育最新版下载地址百人计划

2016年,本科教学优秀奖

2017年,“优秀科技工作者”(中国电子学会颁发)

2017年,bob体育最新版下载地址先进工作者

2017年,bob体育最新版下载地址第四届“我最喜爱老师”卓越风采奖


主讲课程
半导体物理